The present invention relates to a semiconductor memory device, and more particularly to a ZQ calibration of the semiconductor memory device.
Generally, various semiconductor devices implemented by integrated circuits such as CPU, memories and gate arrays are used for various digital products such as personal computers, servers and work stations. For the most part, the semiconductor devices have an input circuit for receiving different signals from an external circuit through input pads and an output circuit for providing internal signals to the external circuit.
Meanwhile, as the operation speed of the digital products becomes higher, the swing width of the signals which are interfaced between the semiconductor devices is decreased. The reason why the swing width is getting narrower is that it is necessary to minimize the transmission time of the signals. However, the narrower the swing width is, the more the semiconductor devices are influenced by the external noise and the more the echo-back signal caused by impedance mismatching is serious at the interface. The impedance mismatching is generated by an external noise, a change of power supply voltage or temperature and a change of manufacturing process of the semiconductor devices. If the impedance mismatching is created, it is difficult to transmit the data in a high speed and the output data from an output terminal of the semiconductor device can be distorted. Therefore, in case that the semiconductor device at the receiving side receives the distorted output signal through its input terminal, the problems such as setup/hold failure or the miss judgment can be caused frequently. Particularly, the semiconductor device, in which the high speed operation is required, employs an impedance matching circuit in the vicinity of a pad within the integrated circuit chip to solve the problems.
Generally, in order to match the impedance between the transmitting and receiving sides, the source termination is carried out by the output circuit at the transmitting side and, at the receiving side, the parallel termination is performed by a termination circuit which is in parallel coupled to the input circuit connected to the input pad. A ZQ calibration refers to a process of producing pull-up and pull-down codes for the terminations based on the fluctuations of the PVT (process, voltage, and temperature) conditions. The resistance (termination resistance of a DQ pad in case of a memory device) of the output or termination circuit is controlled by using the codes which are caused by the result of the ZQ calibration (this is called “ZQ calibration” because the calibration is carried out by using the ZQ node).
Hereinafter, a ZQ calibration which is carried out in a ZQ calibration circuit will be described below.
FIG. 1 illustrates a block diagram of a ZQ calibration circuit of a conventional semiconductor memory device. The conventional ZQ calibration circuit includes a first pull-up resistance unit 110, a second pull-up resistance unit 120, a pull-down resistance unit 130, a reference voltage generator 102, comparators 103 and 104, and pull-up and pull-down counters 105 and 106.
A power supply voltage VDDQ is divided by the first pull-up resistance unit 110 and a reference resistor 101, thereby providing a ZQ voltage to a node ZQ. The reference resistor 101 is connected to a pin ZQ coupled to the node ZQ in the external and typically has resistance of 240Ω. The comparator 103 compares the ZQ voltage to a reference voltage VREF (typically, set to VDDQ/2), which is produced by the reference voltage generator 102, and then produces up/down signals using the comparison result.
The pull-up counter 105 receives the up/down signals and then produces a binary code PCODE<0:N>. The resistance value of the first pull-up resistance unit 110 is controlled by a switching operation of resistors through the binary code PCODE<0:N>. The controlled resistance value of the pull-up resistance unit 110 influences the node ZQ again and this operation is repeated. That is, the first pull-up resistance unit 110 undergoes the calibration so that the total resistance value of the first pull-up resistance unit 110 is the same as the resistance value of the reference resistance 101 (typically, 240Ω), which is called a pull-up calibration.
The binary code PCODE<0:N> generated by the pull-up calibration process is inputted to the second pull-up resistance unit 120, thereby determining the total resistance of the second pull-up resistance unit 120. In similar to the pull-up calibration, the pull-down calibration starts in such a manner that a voltage on a node A becomes the same as the reference voltage VREF by using the comparator 104 and the pull-down counter 106. That is, the total resistance value of the pull-down resistance unit 130 becomes the same as that of the second pull-up resistance unit 120 (pull-down calibration).
The binary codes PCODE<0:N>and NCODE<0:N>which are produced by the above-motioned ZQ calibration (pull-up and pull-down calibration) are inputted into pull-up and pull-down termination units of the output driver which has the same configuration as the pull-up and pull-down resistance units of the ZQ calibration circuit in FIG. 1, thereby determining the termination resistance value.
FIG. 2 illustrates a block diagram of an output driver of the conventional semiconductor memory device. The output driver includes a push-pull amplifier 220 to output data through a DQ pin and a pre-driver 210. The pre-driver 210 drives the push-pull amplifier 220 in response to data DATA. In case that the output data DATA are in a high level, the pre-driver 210 enables an up-signal UP<0:N> so that a pull-up termination unit of the push-pull amplifier 220 are turned on. Otherwise, in case that the output data DATA are in a low level, the pre-driver 210 enables a down-signal DOWN<0:N> so that a pull-down termination unit of the push-pull amplifier 220 are turned on.
The pre-driver 210 receives the pull-up calibration code PCODE<0:N> and the pull-down calibration code NCODE<0:N> generated through the above ZQ calibration. The pre-driver 210 turns on pull-up and pull-down resistance units according to the pull-up and pull-down calibration code, which are included in the pull-up and pull-down termination units respectively. That is, even if the logic level of the data DATA decides whether the high data are outputted by turning on the pull-up termination unit or the low data are outputted by turning on the pull-down termination unit, the number of the pull-up or pull-down resistance units to be turned on in each case is determined by the pull-up and pull-down calibration codes PCODE<0:N> and NCODE<0:N>.
In fact, when the pull-up and pull-down termination resistances are measured after the ZQ calibration of the semiconductor memory device, the resistance values taken by each die are different from each other. This is caused by a difference between the different processes which are carried out in each die or by a difference between the pull-up and pull-down calibration codes PCODE<0:N> and NCODE<0:N> in each die.
However, the above-described conventional semiconductor memory device does not have the scheme for outputting the pull-up and pull-down calibration codes PCODE<0:N> and NCODE<0:N> created as the result of the ZQ calibration action. Therefore, there is a problem in that the reason why the termination resistance values of the output drivers in the dies are different from each cannot be inspected.